RS-422 and RS-485 Standards Overview and System Configurations, Application Report (pdf). If the /SS pin of the master is an output, it can be controlled independently of the SPI system. Also, in the diagram, the master’s /SS (slave select) is configured as an output. To properly operate the network each slave computer executes RS232Silent at startup; thus all of the slave transmitters remain silent individually addressed by the master. When the keyword name is received by the Silence() routine running in the slave, the slave QScreen Controller executes RS485Transmit() to send an acknowledgment to the master (which should now be listening to the serial bus to accept the acknowledgment). This allows you to configure full duplex multi-drop networks in which a single master can sequentially address one of many slaves and start a full-duplex exchange of data. In general RS485 is designed for multi-drop, "daisy-chain" operation over a single twisted pair cable with a nominal characteristic impedance of 120 Ohms.



















Table 11 5 shows the connection diagram for a standard 9-pin serial cable. Table 9-6 shows the connection diagram for a standard 9-pin serial cable. Table 11-5 Serial Cable Connections. The pinout of the Communications Connector (H14) is shown in Table 11 2, and the following diagrams show how these signals map to the two serial communications connectors. These standard 9-pin serial connectors are located on the top edge of the QVGA Controller. The QVGA Controller offers a unique addition to full duplex RS232: it can place its RS232 transmitter into a high impedance silent mode under software control. The SPI control register, SPCR, contains 8 bits which must be initialized for proper control of the QVGA Controller’s SPI (M68HC11 Reference Manual, p.8-7). It also defines three generator interface points (signal lines); A, B and C. The data is transmitted on A and B. C is a ground reference. The SCK pin’s synchronous clock signal has configurable phase, polarity and baud rate so that it can interface to a variety of synchronous serial devices. The CPOL, CPHA, SR1 and SPR0 configure the SCK pin’s clock polarity, clock phase, and clock rate.



















It works on half-duplex communication to implement the function of converting the TTL level into RS-485 level which means it can either transmit or receive at any time, not both, it can achieve a maximum transmission rate of 2.5Mbps. MAX485 transceiver draws a supply current of between 120μA and 500μA under the unloaded or fully loaded conditions when the driver is disabled. This function cannot accept incoming data; consult its glossary entry for details. Function prototypes for this function and other versatile serial I/O routines are defined in the COMM.H header file, and are described in detail in the Control-C Glossary. The primary and secondary serial communications ports are accessible through the QVGA Controller`s 10 pin, dual row Communications Connector (H14) and through the individual Serial 1 and Serial 2 connectors. Most computers conform to IBM PC AT-compatible RS232 interfaces which use 9-pin D-Type connectors, consequently the QVGA Controller brings out its serial ports to two female 9-pin D-Type connectors. While handshaking is still with us, it is usually best to disable it in software (if possible) and/or "loop-back" the pairs of signals (RTS to CTS, DTR to DSR, etc.) While RS232 was rumored to be on the "way out" with the advent of many of the new communications standards, it is still alive and well today.



















You`ll need to determine how to set the address on the converter as well as figuring out what the address is on your RS485 device. R.E.Smith also provides an extensive line of optical/transformer isolated repeaters and multi-port repeaters as well as a series of fiber optic products which provide very high isolation. While RS422 is comparable to RS485, it is limited to unidirectional data traffic, and is terminated only on the end of the line opposite the transmitter. A typical RS485 network can operate properly in the presence of reasonable ground differential voltages, withstand driver contentious situations, provide reliable communications in electrically noisy environments (good common mode rejection using twisted pair cable, shielding provides additional protection), and support thirty-two or more (many IC manufacturers have 1/2, 1/4, 1/8 unit load devices) drivers and receivers on the line. The QED-Forth kernel includes pre-coded drivers that configure and control the SPI for maximum speed data transfers. RESOURCE and the access control functions GET() and RELEASE(). Only one active master may control the network at a time; however, the device that assumes the role of master may change according to an appropriate protocol.



































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